Clement Deschamps
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qbox: GICv2 can be added to cortex-a53 with gic_enable param

... ... @@ -54,6 +54,12 @@
#include "qemu/error-report.h"
#include "qapi/error.h"
#include "qbox/qboxbase.h"
#include "hw/intc/arm_gic_common.h"
#define ARCH_TIMER_VIRT_IRQ 11
#define ARCH_TIMER_S_EL1_IRQ 13
#define ARCH_TIMER_NS_EL1_IRQ 14
#define ARCH_TIMER_NS_EL2_IRQ 10
#define TYPE_CORTEX_A53 "cortex-a53"
#define CORTEX_A53(obj) OBJECT_CHECK(CortexA53State, (obj), TYPE_CORTEX_A53)
... ... @@ -210,13 +216,41 @@ static void cortex_a53_machine_init(MachineState *machine)
{
int i;
CortexA53State *cpus[smp_cpus];
int nb_irqs;
qemu_irq *irqs = NULL;
DeviceState *gicdev;
SysBusDevice *gicbusdev;
int gic_enable = qbox_get_remote_uint_param(qbox_get_handle(), "gic_enable");
/* IRQ, FIQ per core */
irqs = g_new(qemu_irq, smp_cpus*2);
if (gic_enable) {
/* export 256 SPIs */
nb_irqs = 256;
}
else {
/* export 2 irqs per core: IRQ and FIQ */
nb_irqs = 2 * smp_cpus;
}
irqs = g_new(qemu_irq, nb_irqs);
if (gic_enable) {
gicdev = qdev_create(NULL, "arm_gic");
qdev_prop_set_uint32(gicdev, "revision", 2);
qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus);
qdev_prop_set_uint32(gicdev, "num-irq", nb_irqs + 32);
qdev_init_nofail(gicdev);
gicbusdev = SYS_BUS_DEVICE(gicdev);
sysbus_mmio_map(gicbusdev, 0, 0xc8000000);
sysbus_mmio_map(gicbusdev, 1, 0xc8001000);
for (i = 0; i < nb_irqs; i++) {
irqs[i] = qdev_get_gpio_in(gicdev, i);
}
}
for (i = 0; i < smp_cpus; i++) {
CortexA53State *s = CORTEX_A53(object_new(TYPE_CORTEX_A53));
DeviceState *cpudev = DEVICE(&s->cpu);
fetch_qbox_params(s, i);
s->kernel = g_strdup(machine->kernel_filename);
... ... @@ -226,8 +260,32 @@ static void cortex_a53_machine_init(MachineState *machine)
qemu_register_reset(cortex_a53_reset_stage0, s);
cpus[i] = s;
irqs[i*2] = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ);
irqs[i*2+1] = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ);
if (gic_enable) {
int ppibase = nb_irqs + i * GIC_INTERNAL + GIC_NR_SGIS;
int irq;
const int timer_irq[] = {
[GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
[GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
[GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
[GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
};
for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
qdev_connect_gpio_out(cpudev, irq,
qdev_get_gpio_in(gicdev,
ppibase + timer_irq[irq]));
}
sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
sysbus_connect_irq(gicbusdev, i + smp_cpus,
qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
}
else {
irqs[2 * i] = qdev_get_gpio_in(cpudev, ARM_CPU_IRQ);
irqs[2 * i + 1] = qdev_get_gpio_in(cpudev, ARM_CPU_FIQ);
}
}
DPRINTF("Loading %s\n", cpus[0]->kernel);
... ... @@ -241,7 +299,7 @@ static void cortex_a53_machine_init(MachineState *machine)
qemu_register_reset(cortex_a53_reset_stage1, cpus[i]);
}
qbox_export_irq(qbox_get_handle(), irqs, smp_cpus*2);
qbox_export_irq(qbox_get_handle(), irqs, nb_irqs);
}
static void cortex_a53_machine_class_init(ObjectClass *oc, void *data)
... ...