DELBERGUE Guillaume
Committed by KONRAD Frederic
Builds for 2 pipelines failed

Fix VICINTENCLEAR register issue

"A HIGH bit clears thecorresponding bit in the VICINTENABLE Register. A LOW bit has no effect."
PL190 ARM DDI 0181E 3-9

Signed-off-by: Guillaume Delbergue <guillaume.delbergue@greensocs.com>
... ... @@ -67,6 +67,8 @@ class PL190:
void Unimplemented(gs::reg::transaction_type *&tr,
const sc_core::sc_time &delay);
void UpdateIRQ();
void IntEnable(gs::reg::transaction_type *&tr,
const sc_core::sc_time &delay);
void ClearIntEnable(gs::reg::transaction_type *&tr,
const sc_core::sc_time &delay);
void WriteSoftwareInt(gs::reg::transaction_type *&tr,
... ...
... ... @@ -101,7 +101,9 @@ PL190::PL190(sc_module_name name):
PL190_r("FIQSTATUS", "", 0x04, 0, 0);
PL190_r("RAWINTR", "", 0x08, 0, 0);
PL190_r("INTSELECT", "", 0x0C, 0, ~0);
PL190_r("INTENABLE", "", 0x10, 0, ~0);
r.create_register("INTENABLE", "", 0x10, gs::reg::STANDARD_REG |
gs::reg::SPLIT_IO | gs::reg::SINGLE_BUFFER |
gs::reg::FULL_WIDTH, 0, ~0, 32);
PL190_r("INTENCLEAR", "", 0x14, 0, ~0);
PL190_r("SOFTINT", "", 0x18, 0x8, ~0);
PL190_r("SOFTINTCLEAR", "", 0x1C, 0, ~0);
... ... @@ -192,6 +194,9 @@ void PL190::end_of_elaboration()
GR_FUNCTION_PARAMS(PL190, ClearIntEnable);
GR_SENSITIVE(r[INTENCLEAR].add_rule(gs::reg::POST_WRITE, "ClearIntEnable",
gs::reg::NOTIFY));
GR_FUNCTION_PARAMS(PL190, IntEnable);
GR_SENSITIVE(r[INTENABLE].add_rule(gs::reg::POST_WRITE, "intEnable",
gs::reg::NOTIFY));
GR_FUNCTION_PARAMS(PL190, WriteSoftwareInt);
GR_SENSITIVE(r[SOFTINT].add_rule(gs::reg::POST_WRITE, "WriteSoftwareInt",
gs::reg::NOTIFY));
... ... @@ -221,8 +226,8 @@ void PL190::UpdateIRQ()
r[RAWINTR] = r[SOFTINT] | ext_irq;
/* Update IRQStatus: */
r[IRQSTATUS] = ~((uint32_t)r[INTSELECT]) & r[RAWINTR] & r[INTENABLE];
r[FIQSTATUS] = r[INTSELECT] & r[RAWINTR] & r[INTENABLE];
r[IRQSTATUS] = ~((uint32_t)r[INTSELECT]) & r[RAWINTR] & r[INTENABLE].o;
r[FIQSTATUS] = r[INTSELECT] & r[RAWINTR] & r[INTENABLE].o;
/* Update the IRQ line. */
data.value = (r[IRQSTATUS] != 0);
... ... @@ -263,7 +268,15 @@ void PL190::ClearIntEnable(gs::reg::transaction_type *&tr,
const sc_core::sc_time &delay)
{
/* Just clear the int enable register. */
r[INTENABLE] = r[INTENABLE] & ~(r[INTENCLEAR]);
r[INTENABLE].o = r[INTENABLE].o & ~(r[INTENCLEAR]);
this->UpdateIRQ();
}
void PL190::IntEnable(gs::reg::transaction_type *&tr,
const sc_core::sc_time &delay)
{
/* Set the int enable register. */
r[INTENABLE].o = r[INTENABLE].o| r[INTENABLE].i;
this->UpdateIRQ();
}
... ...