KONRAD Frederic
Builds for 1 pipeline passed

fix the bit ranges.

This fixes an odd bug with the bit ranges.

Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
... ... @@ -79,26 +79,26 @@ APB_UART::APB_UART(sc_module_name nm):
uart_r("DATA", "Data register", 0x000, 0x00, 0xFF);
uart_r("STATE", "State register", 0x04, 0x00, 0x00);
r[STATE].br.create("TX_FULL", 0, 1);
r[STATE].br.create("RX_FULL", 1, 2);
r[STATE].br.create("TX_OR", 2, 3);
r[STATE].br.create("RX_OR", 3, 4);
r[STATE].br.create("TX_FULL", 0, 0);
r[STATE].br.create("RX_FULL", 1, 1);
r[STATE].br.create("TX_OR", 2, 2);
r[STATE].br.create("RX_OR", 3, 3);
uart_r("CTRL", "Control register", 0x08, 0x00, 0x3F);
r[CTRL].br.create("TX_EN", 0, 1);
r[CTRL].br.create("RX_EN", 1, 2);
r[CTRL].br.create("TX_IEN", 2, 3);
r[CTRL].br.create("RX_IEN", 3, 4);
r[CTRL].br.create("TX_OR_IEN", 4, 5);
r[CTRL].br.create("RX_OR_IEN", 5, 6);
r[CTRL].br.create("HS_TEST", 6, 7);
r[CTRL].br.create("TX_EN", 0, 0);
r[CTRL].br.create("RX_EN", 1, 1);
r[CTRL].br.create("TX_IEN", 2, 2);
r[CTRL].br.create("RX_IEN", 3, 3);
r[CTRL].br.create("TX_OR_IEN", 4, 4);
r[CTRL].br.create("RX_OR_IEN", 5, 5);
r[CTRL].br.create("HS_TEST", 6, 6);
uart_r("BAUDDIV", "Baud rate divider", 0x10, 0x00, 0xFFF);
uart_r("INTSTATUS", "Interrupt Status Register", 0x0C, 0X00, 0x0F);
r[INTSTATUS].br.create("TX", 0, 1);
r[INTSTATUS].br.create("RX", 1, 2);
r[INTSTATUS].br.create("TX_OR", 2, 3);
r[INTSTATUS].br.create("RX_OR", 3, 4);
r[INTSTATUS].br.create("TX", 0, 0);
r[INTSTATUS].br.create("RX", 1, 1);
r[INTSTATUS].br.create("TX_OR", 2, 2);
r[INTSTATUS].br.create("RX_OR", 3, 3);
/*
* We don't care too much about that it's RO.
... ...